In semiconductor fabrication, one or more masks are used to form patterns onto layers of a semiconductor wafer. In an embodiment of lithography, a light sensitive resist coating is formed over one or more layers to which a pattern is to be transferred. The resist coating is patterned by exposing the resist coating to radiation such as light that selectively passes through an intervening mask comprising the pattern. The radiation causes the exposed or unexposed portions of the resist coating to become more or less soluble. A developer is used to remove relatively more soluble areas leaving a patterned resist. The patterned resist can serve as template for an underlying layer that can be selectively etched. Once the underlying layer is treated, the patterned resist is removed leaving a treated layer corresponding to the pattern. Masks, such as those used in lithography, and layers onto which patterns are formed using such masks should align so that devices, such as integrated circuit, are properly formed within the semiconductor layer and function as intended. In an embodiment, if a via within an interconnect layer is misaligned with a first metal structure within a metal one layer and a second metal structure within a metal two layer, then the via will not form a conductive path that should have been formed between the first metal structure and the second metal structure. Accordingly, alignment marks are used to align masks or layers, and overlay marks are used to evaluate accuracy of such alignment.